The open
silicon design
platform

SiliconSpace provides an all-in-one platform and infrastructure to build, integrate, and explore faster.

Start DesigningBrowse Workshop
Join our Discord

Workshop

0
RTL Designer with code editor and waveform viewer
Design and verify RTL
Write Verilog in a full-featured code editor. Run simulations and inspect waveforms with our integrated viewer.
Synthesis view with schematic viewer
Synthesize your design
Transform RTL into gate-level netlists using Yosys. Visualize schematics and analyze timing.
Place and Route with 3D layout viewer
Implement your design with full customization
Perform place and route with a real PDK, and get true PPA statistics.
Project page with sharing options
Save and share your project, and integrate seamlessly
Save your work and share it with the community. Import others' IPs seamlessly into your design. Fork projects, collaborate, and build on each other's work.

Tool Stack

RTL & Simulation
IcarusVCDviz*
Synthesis
YosysABCnetlistsvg**
Place & Route
OpenROADOpenSTA

* designed for SiliconSpace

** modified for SiliconSpace

FAQ