SiliconSpace

Creating Your First Project

Welcome to SiliconSpace! Let's create your first chip design project.

Click the "Create Project" button in your Workshop
Choose a name for your project - for example, "my-first-chip"
Select the sky130 PDK
Choose an open-source license (MIT is recommended for most projects)
Set visibility to "Public" to share with the community, or "Private" for personal projects
Click "Create Project"

Your project is now ready! You'll be redirected to the project detail page where you can start designing.

Understanding the Interface

Once your project is created, you'll see the project detail page with several key sections:

Project Overview: Name, description, PDK, and visibility status
Branches: Different versions of your design (start with "main" branch)
Open in Space: Click this button to enter the design environment
Tabs: Switch between RTL Designer, Synthesis, and Place & Route workflows

The "Open in Space" button takes you to the integrated development environment where you'll write code and run EDA tools.

Working with the RTL Designer

The RTL Designer is your code editor for hardware design. Here's what you'll see:

Left Panel - File Explorer:

rtl/ - Your Verilog source files
sdc/ - Timing constraint files
testbench/ - Simulation testbenches
synthesis/ - Synthesis flow scripts

Center Panel - Code Editor:

Monaco editor with syntax highlighting
Auto-save functionality
Keyboard shortcuts: Cmd/Ctrl+S to save

Right Panel - Waveform Viewer:

VCDviz, our custom waveform viewer designed for modern browsers
VCD file support for simulation results
Pan and zoom controls
Signal hierarchy browser

Let's create your first Verilog file. Click the "+" button in the rtl/ directory and name it "counter.v":

verilog
module counter(
  input wire clk,
  input wire rst,
  output reg [7:0] count
);
  always @(posedge clk or posedge rst) begin
    if (rst)
      count <= 8'b0;
    else
      count <= count + 1;
  end
endmodule

Writing a Testbench for Simulation

Before synthesis, you may want to verify your design with simulation. Create a testbench file in the testbench/ directory named "counter_tb.v":

verilog
`timescale 1ns/1ps

module counter_tb;
  reg clk;
  reg rst;
  wire [7:0] count;

  // Instantiate the counter
  counter dut (
    .clk(clk),
    .rst(rst),
    .count(count)
  );

  // Generate clock - 100 MHz
  initial clk = 0;
  always #5 clk = ~clk;

  // Required: Dump waveforms for viewing
  initial begin
    $dumpfile("waveform.vcd");
    $dumpvars(0, counter_tb);
  end

  // Test sequence
  initial begin
    rst = 1;
    #20;
    rst = 0;
    #500;
    $finish;
  end
endmodule

Testbench Requirements:

SiliconSpace validates your testbench before simulation. Your testbench must include:

$dumpfile("waveform.vcd") - Specifies the output file for waveform data
$dumpvars(0, module_name) - Dumps all signals from your testbench module

Without these statements, the simulation will not produce viewable waveforms. The module name in $dumpvars should match your testbench module declaration (e.g., counter_tb in the example above).

Running Simulation:

In the RTL Designer tab, select your testbench file from the "Testbench" dropdown
Click "Simulate" to run Icarus Verilog
View the resulting waveforms in the VCDviz panel on the right

Adding Timing Constraints

Before synthesis, you need timing constraints. Create a file in sdc/ directory named "timing.sdc":

Timing constraints tell the synthesis tool:

Clock frequency requirements
Input and output delays
False paths and multicycle paths

Here's a basic SDC file for our counter:

sdc
# Clock definition - 100 MHz (10ns period)
create_clock -name clk -period 10.0 [get_ports clk]

# Input delays (relative to clock edge)
# Assume external logic provides stable inputs 2ns after clock
set_input_delay -clock clk -max 2.0 [get_ports rst]

# Output delays (relative to clock edge)
# External logic expects outputs 1ns before next clock edge
set_output_delay -clock clk -max 1.0 [get_ports count]

# Drive strength and load capacitance
set_driving_cell -lib_cell sky130_fd_sc_hd__buf_1 [all_inputs]
set_load 0.05 [all_outputs]

Running Your First Synthesis

Now that you have RTL code and timing constraints, let's synthesize!

Configure Dynamic Variables:

In the Dynamic Variables panel on the left sidebar, you can configure:

Select your RTL files from the file picker
Enter your top module name
Select your SDC timing constraints file

Infrastructure-managed variables like PDK library files and tool paths are auto-populated and read-only.

Run the Job:

Click the green "Run Synthesis" button
Watch the Results Panel for job status

The synthesis job typically takes 30-60 seconds for small designs.

Viewing Synthesis Results

Once synthesis completes, you'll see:

Interactive Schematic Viewer:

Visual representation of your gate-level netlist
Pan: Click and drag to move around
Zoom: Mouse wheel or zoom buttons
Module hierarchy navigation

Synthesis Report:

Cell count and area metrics
Timing analysis (WNS, TNS)
Power estimates
Optimization statistics

The schematic shows how your RTL code was converted into actual logic gates from the PDK library.

Key Concepts

Before diving deeper, here are essential concepts:

Projects:

Container for your design files and flow configurations
Can be public (shared with community) or private
Belong to a user or organization

Branches:

Parallel versions of your design (like Git branches)
Experiment without affecting your main design
Each branch has independent synthesis/APR configurations

PDK - Process Design Kit:

SiliconSpace uses the open-source sky130 PDK
130nm process node from SkyWater
5 metal layers with 1.8V standard cells
Great for learning and prototyping
Active community support

Flow Scripts:

Define the automation workflow for EDA tools (Yosys, OpenROAD)
Pre-configured templates available
Each flow script defines a variable schema
Some variables are user-editable, others managed by infrastructure

Quick Start Guide