EDA for everyone
From simple modules to complex SoCs. Design chips with open-source PDKs and EDA tools.
| Feature | Free | Student | Plus | Institution |
|---|---|---|---|---|
| Std Cell Instances | 50,000 | 1,000,000 | 1,000,000 | 1,000,000 |
| User Seats | 1 | 1 | 1 | 50 + $1/year each |
| Max Projects | 3 | Unlimited | Unlimited | Unlimited |
| Compute Resources | Basic | Enhanced | Enhanced | Enhanced + Reserved |
| PDK Access | sky130 only | All PDKs | All PDKs | All PDKs |
| Flowscripts | Basic flow | All flowkits | All flowkits | All flowkits |
| Hierarchical Design | — | |||
| Create Organizations | — | |||
| Priority Queue | — | |||
| Admin Dashboard | — | — | — | |
| Reserved Compute | — | — | — | |
| Course Integration | — | — | — | |
| Support Level | Community | Dedicated | ||
| Price | $0forever Start Free | $3per month Verify Student | $6.99per month Upgrade to Plus | $99per month Contact Sales |
Frequently Asked Questions
What are standard cell instances?
Standard cell instances are the individual logic gates (AND, OR, flip-flops, etc.) that make up your chip design. A 50k instance design might be a simple module, while 1M instances could be a complete processor or SoC.
How does pricing work?
SiliconSpace uses simple monthly tiers. You pay a fixed amount and get access to all features in your tier with no surprise charges. Free tier includes 3 projects and 50k cell designs. Paid tiers unlock unlimited projects, larger designs (1M cells), and enhanced compute.
What is the Student plan?
Students with a valid .edu email get full Plus access for just $3/month. Simply register with your .edu address and verify your status.
What's included in Institution support?
Institutions get all Plus features plus admin dashboard for managing users and reserved compute capacity for consistent performance.
Can I upgrade or downgrade anytime?
Yes! Upgrade instantly to access more features. Downgrades take effect at the next billing cycle with no penalties.
What are reserved compute resources?
Institution plans include guaranteed compute capacity, ensuring your jobs run without queuing delays even during peak usage times.
What if my design exceeds 1M cells?
For designs larger than 1M standard cells, use a hierarchical design flow. Break your design into smaller blocks, implement them separately, then integrate them at the top level. This approach is available on Student, Plus, and Institution plans.